![]() We prove that for any constant c there exists a fault-free subgraph of an n-dimensional hypercube with nc faulty components that can implement a large class of hypercube algorithms with only a constant factor slowdown. We then consider hypercubes with both edge and node faults. Using this embedding we can run ascend-descend algorithms (such as bitonic sort) on the faulty hypercube by implementing them on the embedded CCC. ![]() The key to our approach is an efficient method for embedding a fault free Cube Connected Cycles (CCC) graph in the faulty hypercube. We first consider edge faults and show how to tolerate faults with a constant factor slow-down in communication and no slowdown in computation. We present two sets of novel results related to this issue. We examine the issue of running algorithms with a constant factor slowdown on a faulty hypercube in a worst case scenario. Timing models and complexity analysis are verified by experiments on a Boolean-cube-configured multiprocessor. All three spanning trees offer optimal communication times for cases (2)-(4) and concurrent communication on all ports of every processor. With appropriate scheduling and concurrent communication on all ports of every processor, routings based on these two communication graphs offer a speedup of up to n/2, and O( square root n) over the routings based on the spanning binomial tree for cases (2)-(4) respectively. Three communication graphs (spanning trees) for the Boolean n-cube are proposed for the routing, and scheduling disciplines provably optimum within a small constant factor are proposed. The paper presents the algorithm adopted together with basic elements of its implementation and gives typical examples of its usage.įour different communication problems are addressed in Boolean n-cube configured multiprocessors: (1) one-to-all broadcasting: distribution of common data from a single source to all other nodes (2) one-to-all personalized communication: a single node sending unique data to all other nodes (3) all-to-all broadcasting: distribution of common data from each node to all other nodes and (4) all-to-all personalized communication: each node sending a unique piece of information to every other node. The Verification Module compares solutions submitted by students with the one obtained by the Synthesis Module and assigns points in accordance with the algorithm for the assessment of students work. ![]() Teachers use the Synthesis Module to obtain the solution for the task given to students. The task given to students at the exam is to carry out the synthesis of a switching circuit on paper, draw and simulate its structural scheme using the Simulation Module and submit the final design for assessment. The Verification Module makes it possible to teachers to automate the verification and assessment of student's work at the exam. The Synthesis Module and the Simulation Module allow students preparing for the exam in digital logic design first to verify the correctness of each step of the formal design process and then to draw and simulate their own design. The Verification Module has been developed and used at the School of Electrical Engineering, University of Belgrade as part of a system for digital logic design and simulation, which also includes the Synthesis Module and the Simulation Module. The paper describes the Verification Module for automatic assessment and verification of students' work in digital logic design. This paper surveys the research activities in Verilog simulator technologies as well as comparing every technology’s strengths and weaknesses. Researchers are actively studying new improvements and approaches to keep simulators relevant. With increasing circuit design density and complexity, major simulator vendors are struggling to improve simulation throughput in order to maintain quality and engineering cost of product development. ![]() Various forms of software and hardware assisted digital logic simulators were developed ever since the adoption of Verilog in the industry. At every stage along the development, simulations are inevitably needed to verify circuit correctness. Verilog’s ability to model a circuit at different abstraction levels makes it a preferred mode of design entry starting from the conceptual stage till obtaining the final gate level netlist. In order to model such a circuit, Verilog has emerged to be one of the most widely used Hardware Description Languages in digital VLSI design. Digital logic design has become increasingly complex in multi-billion transistor VLSI. ![]()
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